Optimal solutions for cellular neural networks by paralleledhardware annealing

An engineering annealing method for optimal solutions of cellular neural networks is presented. Cellular neural networks are very promising in solving many scientific problems in image processing, pattern recognition, and optimization by the use of stored program with predetermined templates. Hardware annealing, which is a paralleled version of mean-field annealing in analog networks, is a highly efficient method of finding optimal solutions of cellular neural networks. It does not require any stochastic procedure and henceforth can be very fast. The generalized energy function of the network is first increased by reducing the voltage gain of each neuron. Then, the hardware annealing searches for the globally minimum energy state by continuously increasing the gain of neurons. The process of global optimization by the proposed annealing can be described by the eigenvalue problems in the time-varying dynamic system. In typical nonoptimization problems, it also provides enough stimulation to frozen neurons caused by ill-conditioned initial states.     

Evaluation and optimization of query programs in an object-orientedand symbolic information system

OASIS, a database programming environment that extends UNIX with the concept of persistent objects, is discussed. The OASIS query languages extend conventional database query languages with procedural methods and general control statements. As the complexity of the languages makes it difficult to device a query optimizer based on a universally applicable algorithm, each query in OASIS is optimized based on a collection of basic patterns for which each pattern is associated with a separation query optimization algorithm. The optimization techniques for a set of basic patterns consisting of iterative statements and a set of nested statements is described. The optimization techniques discussed include an extended decomposition algorithm, evaluation of multiple conditions, data dependence analysis, and optimization of queries with arbitrary nesting     

Nitride-Based ultraviolet metal-semiconductor-metal photodetectors with a low-temperature GaN layer

The GaN metal-semiconductor-metal (MSM) ultraviolet (UV) photodetectors with a low-temperature (LT)-GaN layer have been demonstrated. It was found that we could achieve a two orders of magnitude smaller, photodetector-dark current by introducing a LT-GaN layer, which could be attributed to the larger Schottky-barrier height between the Ni/Au metal contact and the LT-GaN layer. It was also found that photodetectors with the LT-GaN layer could provide a larger photocurrent to dark-current contrast ratio and a larger UV-to-visible rejection ratio. The maximum responsivity was found to be 3.3 A/W and 0.13 A/W when the photodetector with a LT-GaN layer was biased at 5 V and 1 V, respectively.     

Improved ESD protection by combining InGaN-GaN MQW LEDs with GaN Schottky diodes

GaN Schottky diodes were built internally inside the GaN green LEDs by using etching and redeposition techniques. By properly selecting the etching areas underneath the bonding pads, one can minimize the optical loss due to the etching process. Although the reverse current and the forward turn-on voltage were both higher for the GaN LED with a Schottky diode, it was found that the internal Schottky diode could significantly increase the electrostatic discharge threshold from 450 to 1300 V.     

Fiber Bragg grating dispersion compensator by single-period overlap-step-scan exposure

We theoretically demonstrate that a high-quality fiber Bragg grating dispersion compensator can be fabricated by a properly designed single-period overlap-step-scan exposure method. A practical design example and a detailed tolerance analysis of this new fabrication method are given.     

An efficient VLSI design for a residue to binary converter for general balance moduli (2/sup n/-3,2/sup n/+1,2/sup n/-1,2/sup n/+3)

In this paper, we present a new four-moduli set (2/sup n/-3,2/sup n/+1,2/sup n/-1,2/sup n/+3) and an efficient residue to binary (R/B) converter design. The merits of the proposed four-moduli set include 1) larger dynamic range; 2) higher degree of parallelism for conversion; 3) balanced bit-width for internal RNS arithmetic operations; and 4) flexible moduli set selection. According to the relation between the proposed moduli, the divide-and-conquer technique is used to design a two-level converter architecture which has lower hardware cost and shorter critical delay. For the R/B converter designed with 12-b (n=3), our architecture has about 47% saving in hardware cost and 40% saving in critical delay compared to the last work.     

A Vlsi Neural Network Processor Based on Hippocampal Model

The hippocampal region of the brain system can be analyzed with the nonlinear system modeling approach. The input-output relationship of the neural units is best represented by the kernel functions of different complexities. The modeling expression of the first and second order kernels are computed in analog current-mode instead of digital data processing in order to fully explore massively parallel processing capability of the neural networks. Two distinct methods are utilized: the table-look-up approach and the model-based approach. The former can achieve high accuracy but consumes large silicon area while the latter saves silicon area and maintains moderately high accuracy. Circuit-level simulation results and experimental data from two test structures are presented.     

A general replacement of a system subject to shocks

A system is subject to shocks that arrive according to a nonhomogeneous Poisson process. The system is replaced at age T at a fixed cost c₀. If the k-th shock arrives at time S_k<T, it is either a fatal shock with probability p(S_k) or a nonfatal shock with probability 1−p(S_k). The fatal shock causes the system total breakdown, and the system is replacd at a cost c_∞. The nonfatal shock weakens the system and makes it more expensive to run. The aim of the paper is to find the optimal T which minimizes the long run expected cost per unit time of the policy. Various special cases are considered.